1. Technical Field
The present application relates generally to an improved circuit simulation system and method. More specifically, the present application is directed to a system and method for propagating phase constants in static model analysis of circuits.
2. Description of Related Art
Electronic design automation (EDA) is now commonly used in the design of integrated circuits. EDA makes extensive use of computers to automate the design process. Once a circuit has been designed and physically laid out, extensive testing is performed to verify that the new design and layout will work as desired. Testing of the new design is typically performed by simulating the design using a computer, which permits relatively fast verification of the circuit without necessitating physically placing the design in silicon.
Static analysis and dynamic simulation are two primary conventional methods employed to analyze and verify circuit behaviors of a design. Dynamic simulation provides a relatively close approximation of actual operation of a circuit design but requires extensive time and resources to perform. Static analysis requires less time and resources to perform, but has limitations with regard to the information that may be obtained.
One method of performing static analysis is to constrain the static analysis operation by using constants. For example, when identifying paths between points in the circuit model, constant net values can be used to prune certain paths from consideration. If the traversal leads to a data input of a multiplexer, for example, and the select value enables another data input, then it is known that traversal cannot proceed further. Constants and propagating constant values through nets of a circuit model is an important step in static model analysis.
It is fairly easy to propagate constant values through nets of a circuit model. For example, if an input of an AND gate is 0, then it is known that the output should also be 0. However, for sequential circuit models, such as static circuit models having latches or other sequential circuit elements, constant propagation usually stops at these sequential elements. It is only possible to propagate a value through a latch or other sequential element if the sequential element's “enable” input is a constant 1. For latches, this can be shown by the following expression which is typically used to represent a latch:Latch(t)=clock & data|(^ clock) & latch (t−1)
A more general representation of a latch takes into account the time delays in the latch output using the following expression:Latch(t)=clock(t−td) & data (t−td)|(^ clock(t−td)) & latch (t−td)where td is a latch update delay amount. This general expression accounts for situations in which the values used to compute the latch output value during a particular phase may be from a preceding phase in the analysis. If the delay amount is less than a phase, one can “abstract away” the td value. However, the previous latch value must be from the previous phase and thus, if t is in whole units of phases, the previous latch value is latch(t−1). This results in the original latch expression above. The original simplified latch expression should not be used if the time delay for a latch update is better represented as a phase or multiple phases, or if various latch delays are employed in the model such that they are best represented with different phase delays.
From these expressions it can be seen that a problem arises due to the fact that the enable/clock input of a latch is oscillating and the latch stores/outputs values when clocked and retains old values when not clocked. Thus, in static analysis, where inputs are not clocked, and hence, there is no temporal dimension to the static analysis when propagating constant values through the circuit model, it cannot be determined what the output of a latch is since it is not possible to know what the latch's old value is. As a result, constant propagation halts at sequential elements and thus, a full understanding of the operation of the circuit cannot be obtained from static analysis.